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CSIP:SystemC 2 Verilog
类型:软IP
简短描述:SystemC 2 Verilog
详细描述:

SystemC is a powerful language that allows the designer to develop a complete system description of his design.

From this system level design is necessary to get down to a RT synthesizable description that allows a physicall implementation of the model. But at this point there is a lack of synthesis tools that get a SystemC RT description as input. That means it is necessary a translation step to a supported HDL, that means Verilog or VHDL. Due to the similitude of Verilog and C it looks reasonable to convert the SystemC RT description to a Verilog equivalent one.

 


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