首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
MIPI D-PHY

公司: WWAGO

联系人:jessie li

邮箱: jessie.li@wwago.com

产品简介:

General Description:
The MIPI D-PHY IP is a high-frequency low-power, low-cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Although it is primarily used for connecting cameras and display devices to a host processor, it can also be used for many other portable applications. It is used in a master-slave configuration. High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Feature:
• Complies with MIPI Standard for D-PHY V 1.0
• Point-to-point differential interface supporting multiple data lanes and a clock lane
• Supports both high speed and low-power modes
• Data lanes support both bidirectional and unidirectional modes
• Clock lane supports unidirectional communication
• 80 Mbps to 1Gbps data rate in high speed mode
• 10 Mbps data rate in low-power mode
• Modular design to allow for all possible configurations
• Low power dissipation

    C*Core:RTC     C*Core:PORTS Module
分享到: