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Verisilicon:S13_DLL_01
类型:硬IP
简短描述:533M, 50ps jitter
详细描述:

The S13_DLL_01 is developed as a macro cell to generate two independent channels?programmable delay. The master block is the core DLL, which takes reference clock as input, running at DDR or DDR2 speed. The slave block consists of two 90 degrees delay lines which are controlled by Master block and the adjust pin. The slave block provides 2 output signals, each one is of 90 degrees delay to its DQS input signal, and renders minor delay tuning.


工艺:0.13um
代工厂:SMIC
应用:
特色:

Process: SMIC 0.13um Generic 1P 6/7/8M 
Single power supply: 1.2V 
Reference frequency range: 200 MHz to 533.3 MHz 
Programmable delay tuning around DQS抯 90 degree delay. 
Low jitter output (less than 100ps for DDR or 50ps for DDR2 cycle to cycle jitter) 
Matching rise and fall time on the output signals.

    Verisilicon:S13_DCXO_01_L     Verisilicon:S13_OTG_PHY_01
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