首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
CAST Inc.:DDR2-SDRAM-CTRL
类型:Soft IP
简短描述:DDR/DDR2 SDRAM Memory Controller Core
详细描述:

The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:

  • Simplicity. All required management, initialization, address and burst handling procedures are done by the core. The control, write-data, and read-data paths are split, enabling higher performance and easier integration.
  • Performance. The core achieves maximum bandwidth utilization through pipelined and parallel architectural design practices.
  • Flexibility. All memory parameters (timing parameters, memory size parameters, mobile-DDR support, auto-refresh policies, etc.) are runtime configurable.
  • Easier Integration. Most necessary related components—DDR/DDR-II Controller, data-path FIFOs, DLLs—come built into the core, and some FPGA versions even include a PHY.
  • The core has been carefully designed and rigorously verified, and is delivered with comprehensive documentation and a complete verification environment.


    工艺:0.18 μm, 0.13 μm, 0.09 μm
    代工厂:TMSC
    应用:1)Processor Interfaces 2)Networking 3)Video / Image Processing
    特色:
  • Interfaces to all industry standard DDR and DDR-II SDRAM DIMMs and chips, including Mobile DDR SDRAMs.
  • High-performance architecture, with a three-stage processing queue for maximum bandwidth utilization.
  • Pipelined design facilitates integration and enables high clock rates.
  • Includes power-down and self-refresh, critical for low-power applications.
  • Datapath logic with small FIFOs, enables handshaking mechanism for enhanced performance and easier integration.
  • Two different PHY implementations available: an advanced delayed-DQS capture mechanism with per-bit deskew, and a delayed-clock capture with dual-port synchronizing FIFO.
  • Utilizes per-bank status monitoring.
  • Incorporates a programmable auto-precharge mechanism.
  • Incorporates a programmable automatic refresh policy.
  • Supports up to eight chip-selects, up to eight banks per chip, twelve to fifteen row bits, and nine to twelve columns bits.
  • Runtime-configurable parameters ensure flexibility: eleven timing parameters, CAS latency, Burst Length, Row bits, Column bits, Bank bits, number of CSs, Extended-Mode-Registers’ values, registered-DIMM support, power-saving and auto-precharge mechanism activation.
  • Flexible user-interface, with split command, write-data and read-data paths. All paths support hand-shaking mechanisms.
  • Multi-burst access support: access requests can have any size burst lengths from 1 to 65536; the core segments these into an appropriate number of SDRAM bursts.
  • cast-ddr2-sdram-ctrl.rar

        CAST Inc.:SDR-SDRAM-CTRL     CAST Inc.:C8237
    分享到: