首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
上海硕讯微电子:基于CORDIC算法迭代结构Sin Cos计算IP软核
类型:软IP
简短描述:ESSINCOS1601是一种采用面向于ASIC的,用可综合的Verilog HDL语言风格进行设计的基于CORDIC算法的迭代结构设计的实现计算Sin Cos功能的IP软核。
详细描述:

The ESSINCOS1601 core is the Verilog HDL synthesizable model to implement the function of calculating sine cosine.The core is a digital signal processing block, working on 16 bits of data at a time. The whole calculation process are performed in 24 clocks. The design uses the iterative structure,so the area of the core is very small.The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.


工艺:
代工厂:
应用:
特色:

Using CORDIC algorithm; 

Simple interface and timing

Fully Synchronous design. All inputs and outputs are based on the rising edge of clock

Iterative structure

Small gate count

The whole calculation process are performed in 24 clocks


SinCos01_eSolutions.rar

    上海硕讯微电子:基于CORDIC算法流水线结构Sin Cos计算IP软核     AST:AST DES Core - Data Encryption Standard (DES) Core
分享到: