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上海硕讯微电子:基于CORDIC算法流水线结构Sin Cos计算IP软核
类型:软IP
简短描述:ESSINCOS1602是一种采用面向于ASIC的,用可综合的Verilog HDL语言风格进行设计的基于CORDIC算法流水线结构实现的计算Sin Cos功能的IP软核。
详细描述:

The ESSINCOS1602 core is the Verilog HDL synthesizable model to implement the function of calculating sine cosine.The core is a digital signal processing block, working on 16 bits of data at a time. The whole calculation process are performed in 28 clocks. The design uses the pipeline structure,so the data processing speed of the core is very fast.The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.


工艺:
代工厂:
应用:
特色:

Using CORDIC algorithm

Simple interface and timing

Fully Synchronous design

Pipeline structure

High performance,high data throughput

The whole calculation process are performed in 28 clocks

Through the FPGA board-level verification


SinCos02_eSolutions.rar

    上海硕讯微电子:基于CORDIC迭代结构双曲Sinh Cosh计算IP软核     上海硕讯微电子:基于CORDIC算法迭代结构Sin Cos计算IP软核
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