首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
Aurora VLSI, Inc.:AU-SS4000
类型:软IP
简短描述:Multilayer AMBA Bus Interconnect
详细描述:

The Multilayer AMBA Bus Interconnect provides a configurable multilayer AMBA AHB Bus
interconnect. It can be configured as a two to sixteen layer AMBA AHB Bus interconnect. Up to
63 AMBA AHB Bus masters and 63 AMBA AHB Bus slaves can be supported. The read and
write data widths are user configurable to either 32 bits or 64 bits. The Multilayer AMBA Bus
Interconnect is available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• 2 to 16 layer AMBA AHB bus interconnect- user configurable
• 32 bit or 64 bit data widths- user configurable
• 1 to 63 AMBA Bus masters- user configurable
• 1 to 63 AMBA Bus slaves- user configurable
• 0 to 15 AMBA Bus masters per AMBA AHB bus
• 0 to 15 AMBA Bus slaves per AMBA AHB bus
• Fully pipelined for highest throughput
• Low bus to bus latency
• Supports all required AMBA AHB bus features
• Supports all AMBA AHB bus responses- OKAY, ERROR, RETRY, SPLIT
• Unused AMBA AHB bus layers, AMBA Bus master interfaces, AMBA Bus slave
interfaces, AMBA Bus address registers, decoders, arbiters, etc. are not in the
synthesized netlist to minimize gate count.

    Aurora VLSI, Inc.:AU-B3000     Aurora VLSI, Inc.:AU-G0100
分享到: