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Aurora VLSI, Inc.:AU-B3000
类型:软IP
简短描述:AMBA AHB Bus Master Core
详细描述:

The AU-B3000 AMBA AHB Bus Master provides the bus master function for the AMBA AHB
Bus. It accepts requests from the user’s logic and turns them into AMBA Bus transactions on the
AMBA AHB Bus. The AMBA AHB Bus Master is available as a synthesizable Verilog model
from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• AMBA AHB Bus master function
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Fully pipelined for highest throughput
• Supports all required AMBA AHB Bus features
• Simple request/acknowledge and valid/ready requester interface protocols
• Write abort to terminate writes early
• AMBA Bus read error returned to the user with the read data
• Big endian and little endian modes

    Aurora VLSI, Inc.:AU-B2000     Aurora VLSI, Inc.:AU-SS4000
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