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Aurora VLSI, Inc.:AU-B2000
类型:软IP
简短描述:AMBA AHB Bus Slave Core
详细描述:

The AU-B2000 AMBA AHB Bus Slave provides the bus slave function for the AMBA AHB
Bus. It is used to connect a device in the user’s logic to the AMBA Bus. It accepts AMBA Bus
transactions that target the device and only passes the transactions that require data transfers, to the device in the user’s logic. AMBA Bus transactions that do not transfer data- IDLE and BUSY, are handled entirely within the AMBA Slave. Additionally, the AMBA Slave also performs other AMBA Bus protocol functions so that the device does not have to implement these functions. The AMBA Bus Slave is available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• AMBA AHB Bus slave function
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Handles all IDLE and BUSY transactions without any user logic
• Automatic RETRY when the user’s device is not ready
• Implements AMBA Bus timeout and RETRY response
• Supports all required AMBA AHB Bus features
• Informational signals to support read data prefetching, write data packing, and splits
• Same cycle device request/response is supported for highest throughput
• Independent read and write data buses from/to the device
• Handles all data alignment for data transfer sizes less than the AMBA Bus width
• User configurable for big or little endian AMBA Bus- transparent to the device
• Data transferred regardless of response type

    Aurora VLSI, Inc.:AU-B1000     Aurora VLSI, Inc.:AU-B3000
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