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Aurora VLSI, Inc.:AU-B0002
类型:软IP
简短描述:AMBA AHB/AHB Bus Bridge Core
详细描述:

The AMBA AHB/AHB Bus Bridge is a unidirectional bridge between two AMBA AHB buses.
It drives a transaction from a source AMBA AHB bus to a destination AMBA AHB bus. A full
bidirectional bridge is implemented using two AMBA AHB/AHB Bus Bridges in parallel, with
each pointing in the opposite direction of the other. The AMBA AHB/AHB Bus Bridge is
available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• Unidirectional source AMBA bus to destination AMBA bus bridge function
• Bidirectional bridge implemented with two instantiations
• 32 bit or 64 bit source AMBA bus- user configurable independent of destination
AMBA bus width
• 32 bit or 64 bit destination AMBA bus- user configurable independent of source
AMBA bus width
• 64 destination AMBA bus address spaces
• Supports all AMBA bus transaction types
• Supports all AMBA bus burst types
• Supports AMBA bus data sizes of 1, 2, 4, and 8 bytes
• Supports all AMBA response types
• Automatic destination AMBA bus retries after RETRY and SPLIT responses on the
destination AMBA bus
• Source AMBA bus transaction timeout detection, and subsequent RETRY or SPLIT
response when
- there is no room for write data
- upon long latency read data
• Efficient use of the destination AMBA bus
- packs write data from the source AMBA bus
- unpacks read data from the destination AMBA bus
• Low latency and fully pipelined for highest performance
• Synchronous or asynchronous source and destination AMBA AHB bus clocks

    Aurora VLSI, Inc.:AU-B0001     Aurora VLSI, Inc.:AU-B0003
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