首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
Aurora VLSI, Inc.:AU-B0001
类型:软IP
简短描述:AMBA AHB/APB Bus Bridge Core
详细描述:

The AMBA AHB/APB Bus Bridge is a bridge between an AMBA AHB Bus and an AMBA APB
Bus. It includes the slave select line decoder for the AMBA APB Bus. Sixteen AMBA APB Bus
slaves are supported. The AMBA AHB/APB Bus Bridge is available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• AMBA AHB Bus to APB Bus bridge function
• AMBA APB Bus decoder function
• 16 AMBA APB Bus slaves
• Supports all AMBA AHB Bus transaction types
• Supports all AMBA AHB Bus burst types
• Supports AMBA AHB data sizes of 1, 2, and 4 bytes
• 16 slave address registers- one register per slave
- base address of the slave’s address space
- size of the slave’s address space
• Synchronous or asynchronous AMBA AHB bus clock and AMBA APB bus clock

    Aurora VLSI, Inc.:AU-B0000     Aurora VLSI, Inc.:AU-B0002
分享到: