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Aurora VLSI, Inc.:AU-B0000
类型:软IP
简短描述:AMBA AHB Bus Core
详细描述:

The AU-B0000 AMBA AHB Bus provides the muxes that implement the AMBA AHB Bus as
described in the "AMBA Specification 2.0". The read and write data widths are user configurable
to either 32 bits or 64 bits. The number of AMBA Bus masters and slaves connected to the
AMBA AHB Bus is also user configurable, up to sixteen of each. The AMBA AHB Bus is
available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• AMBA AHB Bus
• 32 bit or 64 bit data widths- user configurable
• 1 to 16 AMBA Bus masters- user configurable
• 1 to 16 AMBA Bus slaves- user configurable
• Default master- Master 0
• Default slave- Slave 0
• User can optionally supply the default master and/or default slave
• Seamless connections to AMBA AHB Master, AMBA AHB Slave, AMBA AHB
Bus Arbiter/Decoder, and AMBA AHB/APB Bus Bridge from Aurora VLSI.

    Verisilicon:SMIC25_USB11_02     Aurora VLSI, Inc.:AU-B0001
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