首 页
韦德国际官网1946介绍
新闻中心
政策法规
技术服务
招商合作
公共服务
孵化器
招贤纳士
联系我们
    > 技术服务
公共EDA平台
设计服务平台
MPW流片服务
芯片测试分析
芯片封装
IP交易中心
    > 服务平台
  您当前的位置:首页 > 技术服务 > IP交易中心   
分 类 开源IP/免费下载  |   推荐IP核  |   Physical Library  |   Analog & Mixed Signal  |   Arithmetic & Mathematic  |   Controllers  |   Peripheral Cores  |   Interfaces  |   Bus  |   Digital Signal Processing  |   Processors & Microcontrollers  |   Memory Element  |   Security / Error Corr. Det. / Modulation  |   Multimedia / Video / Image / Audio  |   Wireline Communications  |   Wireless Communications  |   Platform Level IP  |   Software IP  |   FPGA IP  |   Other  |   Verification IP  |  
Verisilicon:S13V33_USB20PHY_01
类型:硬IP
简短描述:Hi-Speed USB UTMI-Based Peripheral Transceiver IP
详细描述:

The USB 2.0 PHY is a Hi-Speed Universal Serial Bus (USB) peripheral transceiver IP based on the Intel?USB 2.0 Transceiver Macrocell Interface (UTMI) standard. It provides the complete solution of physical layer (PHY) functionality for a Hi-Speed or full-speed USB chip. Designed to seamlessly integrate with Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs), the USB 2.0 PHY simplifies the design process and speed time-to-market. Because UTMI is a proven, standardized implementation of the transceiver, the products integrated with USB 2.0 PHY are easier to test and offer wider interoperability. The USB 2.0 PHY has a parallel, bidirectional data interface with 8/16 bits width that complies with the UTMI standard. It supports data transfer at high-speed (480 Mbps) and full-speed (12 Mbps) rates, so it can operate in USB devices of either type.


工艺:0.13um
代工厂:SMIC
应用:
特色:

Compliant with USB Spec Rev2.0 
Compliant with UTMI Spec Rev1.05 
Support 480Mbit/s 揌igh Speed?and 12Mbit/s 揊ull Speed? 
Support 60MHz/8-bit unidirectional interface and 30MHz/16-bit bidirectional interface. 
12MHz external crystal, internal oscillator and PLL are used to generate high-speed internal clock and CLKOUT output. 
Internal terminations include 1.5Kohm pull-up resistor switching on DP/DM in the FS state and the HS chirp state. 
Clock and data recovery from serial stream on the USB bus. 
Support detection of USB reset, suspend, resume and remote-wake-up features. 
Support test modes defined in USB2.0 Specification. 
NRZI and Bit Stuff encoding and decoding.

    Verisilicon:GSMC18_USB11_01_L     Verisilicon:S13V33_USB20PHY_03
分享到: